Semiconductor devices may include integrated circuitry; such as, for example, integrated memory, integrated logic, integrated sensors, etc. Fabrication of the integrated circuitry often involves complex processing steps. During the manufacture of integrated circuitry, many layers of different materials may be applied one atop another. These layers must be accurately registered to ensure proper operation of the semiconductor device. If the layers are not properly aligned, the device may not perform well, or may be inoperative.
To aid in the registration of overlying layers in semiconductor devices, alignment marks (i.e., registration marks) are included in various layers during fabrication. The alignment marks have a predetermined relationship when they are correctly registered. A reticle is used to pattern the appropriate marks on a particular wafer process layer.
A problem encountered during the utilization of alignment marks is that some of the process steps utilized for fabrication of integrated circuitry may undesirably modify the alignment marks. For instance, chemical-mechanical polishing (CMP) may be utilized as a process step during fabrication of integrated circuitry. The polishing may problematically remove portions of the alignment marks in polished layers. Such modifies the alignment marks, leading to difficulties in subsequently utilizing the alignment marks to achieve appropriate registration relative to other layers stacked over the polished layers. It would be desirable to develop methods and structures which overcome such problem.